Method for performing dead-zone quantization in a single processor instruction
US5845112A · kind A · utility
25Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Mar 6, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Mar 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T9/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An extension to existent vector instruction sets is presented in a form of new vector instructions which perform operations specialized for efficient digital video compression and decompression. A processor is designed to implement the arithmetic operation of each of these instructions in a single clock cycle, and some of the present instructions perform arithmetic operations selectively and directly on elements of the same registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.