Method for transmission of isochronous data with two cycle look ahead
US5845152A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Mar 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for the loading and unloading of a FIFO in an isochronous transmission mechanism uses descriptor blocks which have both branch addresses and skip addresses. The method can recover from cycle loss by selectively resending or skipping a packet that should have been sent in the lost cycle. The method also works two cycles ahead of schedule, in an attempt to keep the FIFO loaded with all of the packets for two cycles of transmission. The FIFO is filled according to a DMA algorithm and drained according to a Link algorithm where the two algorithms are coordinated to communicate information about lost cycles and current demands or opportunities for transmission. If the Link algorithm detects a lost cycle, it communicates that to the DMA algorithm and the DMA algorithm seeks to compensate appropriately. These two algorithms describe mechanisms for the DMA and Link sides of an isochronous transmitter. Working in parallel, these two units can transmit isochronous packets on a serial bus, with two-cycle workahead, while supporting various recovery mechanisms for dealing with cycle loss. Each of the isochronous channels being transmitted by this system can use the recovery mechanisms…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.