Memory interface for asynchronous transfer mode segmentation and reassembly circuit
US5845153A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1995 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Jul 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) circuit uses a memory map which accommodates a variety of memory sizes. The SAR circuit generates address signals according to the memory map which is independent of memory size. The most significant bits (MSBs) of the address are ignored for memories having fewer address terminals than the SAR circuit. The memory map allocates N-bit addresses to buffers and an expansion area. A first buffer has addresses with i+1 MSBs set to 1 and a second buffer has addresses with i+1 MSBs set to 0. i MSBs can be ignored without causing address conflicts because an address for the first buffer has at least one bit that differs from a corresponding bit in an address for the second buffer. The first and second buffers expand, as required, into the expansion area between the buffer. For an application using the smallest memory, conflicts do not occur because the first and second buffers are sufficient for the minimum memory applications. Typically, buffers adjacent the expansion area contain information describing channels of an ATM network and expand into the expansion area if the network has more than a predetermined number of c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.