Method and device for interconnecting integrated circuits in three dimensions
US5847448A · kind A · utility
30Cited by
16References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1996 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Nov 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and device for interconnecting stacked semiconducting plates, in which each of the plates has an integrated circuit. The semiconducting plates (P) are stacked and made solid with each other. In one embodiment, their connecting contacts are connected by a wire (F) to any one of the faces of the stack except one (B), which is to be in contact with a printed circuit. Connections of the plates together and with the printed circuit is made on the faces (F.sub.V, F.sub.S, F.sub.L) of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.