Semiconductor package and device having heads coupled with insulating material
US5847458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1997 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | May 19, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package includes a plurality of leads and a stage, for mounting a semiconductor chip, arranged in juxtaposition at predetermined spatial intervals. A protruding terminal is formed at a predetermined portion on the lower surface of each of the leads. An insulating material is deposited in a continuous layer on the upper surfaces and the side surfaces of a plurality of the leads and on the side surfaces of the stage. A plurality of the leads and the stage are integrally coupled to each other through the insulating material and, therefore, the upper surfaces of the leads, the upper surface of the stage for bonding a semiconductor chip, and the terminals on the lower surfaces of the leads are exposed outside the insulating material. A semiconductor chip is bonded on the upper surface of the stage, the electrodes of the chip are electrically connected to the terminals on the upper surfaces of the leads, and the upper surface of the stage and the upper surfaces of the leads are deposited with a sealing insulating material thereby to seal the semiconductor chip in the sealing material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.