Multi-stage high-gain high-speed amplifier
US5847600A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1996 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Apr 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45682
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy. The common mode level at the output of the second stage is controlled by injecting a pair of control currents (representative of the difference between a common-mode level actually at the output of the second stage and a desired common mode level) into a pair of mirror input nodes in the second stage. The common mode level of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.