Low voltage CMOS amplifier output stage
US5847606A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 1997 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45508
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS amplifier output stage including a complementary output MOSFET transistor pair whose channels are connected together in series between a supply voltage and a reference potential, and whose gates are driven by a complementary MOSFET level shifting transistor pair and by bias voltage and current circuitry. Preferably, the level shifting transistor pair is a diode-connected NMOS transistor and a diode-connected PMOS transistor, the bias circuitry includes a source follower which drives the source of one of the diode-connected transistors with a current determined by an input voltage, all active elements of the invention are MOSFET transistors, and the minimum supply voltage required for operation is (V.sub.GS +2V.sub.SAT), where V.sub.GS is the largest source to gate voltage of the MOSFET transistors and V.sub.SAT is the largest source to drain voltage of the MOSFET transistors during operation in the saturation region. This allows operation with a supply voltage as low as 1.8 volts with MOSFET transistors suitable for typical applications. The quiescent output current is well controlled and is determined by the device sizes of the MOSFET transistors. The invention can be imple…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.