Integrated circuit design system and method for generating a regular structure embedded in a standard cell control block
US5847969A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1996 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.