Pass gate decoder for a multiport memory dEvice that uses a single ported memory cell array structure
US5848019A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a last stage decoder that generates a local word line signal within a bank of a single-ported memory cell array structure. The decoder inputs predecoded global row address signals, as well as predecoded local row address signals. In order to generate the local word line signal, and thus access a memory cell within a given bank, both one predecoded global row address signal, as well as one predecoded local row address signal must be present. The predecoded local row address signal turns on a pass gate transistor, and allows the predecoded global row address signal to pass through the pass gate transistor and create the local word line signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.