Compiler having automatic common blocks of memory splitting
US5848275A · kind A · utility
8Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.