High speed, direct register access operation for parallel processing units
US5848276A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1995 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Nov 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a computer system having a plurality of parallel processor units with each processor unit associated with at least one register for receiving data for the processor unit. The computer system has a bus unit, coupled to the output of each processor unit and the associated register of each processor unit, to transfer the output data of a first processor unit into an associated register of a second processor unit in a single computer operation. The second processor unit is prevented from reading the associated register until the bus unit transfers the output data from the first processor unit to the second processor unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.