Method and apparatus for caching state information within a directory-based coherency memory system
US5848434A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1996 |
| Grant date | Dec 8, 1998 |
| Priority date | — |
| Expiry date | Dec 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time. The state cache can be a direct mapped cache wherein state information for an associated line of memory is stored within the state cache together with a tag field being a first portion of the address of the associated line of memory, and indexed within the state ca…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.