Method of fabricating a bottom electrode with rounded corners for an integrated memory cell capacitor
US5849624A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1996 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Jul 30, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved stacked capacitor with rounded corners for increasing capacitor breakdown voltage, and a method of constructing the same. The preferred method comprises rounding corners of a container-shaped bottom electrode. In particular, sharp corners of a pre-fabricated conductive silicon container are exposed to an ammonium hydroxide/peroxide mixture. The slow etching effect of the clean rounds angled surfaces thereby minimizing the high field effects usually associated with corners and other angled surfaces. Reducing such field effects by reducing or eliminating sharp corners helps prevent breakdown of the capacitor structure dielectric. Where the conductive container includes a rough layer, such as hemispherical grained silicon, the invention provides the additional advantage of separating individual hemispherical grains, thus allowing later deposition of a uniformly thick dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.