Bus timing protocol for a data storage system
US5850528A · kind A · utility
4Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an data storage system having a bank of disk drives an addressable memory has a buffer memory coupled to a bus, a random access memory coupled to the buffer memory, an internal clock, and a logic network. The logic network is coupled to the bus and configured to transfer data among the buffer memory, the random access memory, and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. The addressable memory is included in an interface and further includes a master memory unit and a slave memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.