Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation
US5850537A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1997 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Feb 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously. Previously, the calculations and communications were divided into discrete phases within each emulation clock period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.