Optimization apparatus for removing hazards by arranging instruction order
US5850552A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1996 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Apr 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimization apparatus is provided for removing hazards from a program by rearranging instructions for each program segment. The apparatus comprises: a Directed Acyclic Graph (DAG) generating means for generating DAGs for each program segment; a hazard marking means for marking hazard-including combinations of a parent instruction and a child instruction in the DAGs for hazard; and a rearranging means for rearranging the instructions for each program segment so that instructions are inserted between the instructions of each marked combination, wherein the inserted instructions do not destroy values stored in resources used by the instructions of the marked combination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.