Personal computer apparatus and method for monitoring memory locations states for facilitating debugging of post and BIOS code
US5850562A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1994 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3698
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A monitor and debugger routine operable on a personal computer for facilitating the design of power-on self-test (POST) and basic input and output system (BIOS) code. The monitor and debugger routine is invoked by POST code early in the system initialization process, before most of the system hardware devices have been initialized and before the operating system has been invoked. The monitor and debugger routine uses minimal system resources--lower memory and a serial communications controller--and is accessed via an external communications and display device connected via a serial communications link generated by the serial communications controller. As so invoked, the monitor and debugger routine can be used to facilitate the design and debugging of the remaining portions of the system initialization code, hardware interface code, suspend and resume code, video code, and other code that cannot be debugged using standard debuggers that require a functioning BIOS and an operating system to operate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.