Polishing method for SOI
US5851846A · kind A · utility
34Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1995 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a dielectric isolation substrate, an end point of a polishing process for selective polishing for forming an SOI layer is detected with a high precision. When polishing a wafer with a polishing pad, the temperature of a region of the polishing pad having polished the wafer at a position immediately thereafter is detected by a temperature sensor and the selective polishing process is ended by discriminating that the rate of variation in the detected temperature has changed from a positive to a negative state and then to a fixed saturated state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.