Method of fabricating BiCMOS devices
US5851864A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1997 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Oct 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.