Method of vertically integrating microelectronic systems
US5851894A · kind A · utility
56Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 3, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating vertically integrated microelectronic systems by CMOS-compatible standard semiconductor process technology, by independently processing individual component layers of at least two separate substrates, including the formation of via holes penetrating through all existing component layers and connecting together the front surfaces of the two substrates, thinning the reverse surface of one of the substrates down to the via holes, increasing the depth of the via holes to a metallization plane of the other substrate and forming electrically conductive connections between the two substrates through the via holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.