Integrated circuits for low power dissipation in signaling between different-voltage on chip regions
US5852370A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5). A first inverter (5526) is connected between first supply voltage (3.3v) and ground and has a first inverter input (IN) and a first inverter output. A second inverter (5518) is connected between second supply voltage (5v) and ground and has a second inverter input (INT) and a second inverter output (OUT). A first feedback transistor (5520) has connections to the second supply voltage (5v), and to the second inverter input (INT) and the second inverter output (OUT). A second feedback transistor (5524) has connections to ground, and to the second inverter input (INT) and the second inverter output (OUT). First and second open-type inverters (5522, 5528) are connected to ground and each of the open-type inverters has an input and output. The input of the first open-type inverter (5522) is connected to the first inverter (5526) input (IN), and the output of the first open-type inverter (5522) is connected to the second inverter in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.