Content addressable memory multiple match detection circuit
US5852569A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1997 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | May 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method for detecting the presence of multiple active match lines in a content addressable memory is disclosed. The circuit includes at least one bus group for expressing a unary-encoded address portion of an active match line and, for each match line, an encoding circuit capable of activating a single member of each bus group according to the address of that match line when that match line is active. The multiple match detection circuit advantageously uses the property that each match line has a unique address, and therefore if there is more than one active match line, at least one bus group will have at least two active members. The multiple match detection circuit further comprises, for each bus group, an bus group detection-OR circuit for computing the logical bus group detection-OR of the members of that bus group. The multiple match detection circuit further comprises an OR circuit for computing the logical OR of the outputs of the bus group detection-OR circuits, for providing a multiple match flag which is active when two or more match lines are active and which is inactive otherwise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.