Simplified architecture for defuzzification integrated circuit (IC) processor including circuits for estimating effective areas without overlapping errors
US5852708A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Jul 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital defuzzification processor implemented as integrated circuits (ICs). The defuzzification IC processor includes an input port for receiving a plurality of input values and a corresponding set of specific weight and an effective area for each of the input values. The defuzzification IC processor further includes a multiplier for multiplying each of the input values to the corresponding specific weight for generating a plurality of partial-input-weighted-specific-weight, the multiplier further multiplying the each of the input values to the corresponding effective area for generating a plurality of partial-input-weighted-effective-area. The defuzzification IC processor further includes an accumulator for adding each of the plurality of partial input-weighted-specific-weight for generating a summed-input-weighted specific-weight, the accumulator further adding each of the plurality of partial-input-weighted-effective-area for generating a summed-input weighted-effective-area. The defuzzification IC processor further includes a divider for dividing the summed-input-weighted-specific-weight by the summed-input-weighted-effective-area for generating a crisp output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.