Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
US5852726A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1995 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.