VLIW processor which processes compressed instruction format
US5852741A · kind A · utility
20Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | May 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLIW processor uses a compressed instruction format that allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.