Reduced-particle method of processing a semiconductor and/or integrated circuit
US5854138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/022
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A semiconductor and/or integrated circuit is provided having reduced particulate count upon or within the circuit. During power ramp down post etch or deposition, particles which formed within the plasma used to effectuate etch or deposition are gradually swept from the region above the integrated circuit. Plasma, and more specifically, the field which forms the plasma is maintained but at reduced levels to allow gradual reduction of particles through a multitude of steps. The steps culminate in eliminating power to the electrodes and plasma between the electrodes. However, at the time at which power is absent, only a few of the original particles remain in the critical region above the integrated circuit. Residual particles can be removed in a purge step following the successive sequence of ramp down steps. Gap between the electrodes is increased to a final position early in the ramp down sequence so that additional electrode movement does not occur when the field is weakened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.