Low power latch requiring reduced circuit area
US5854565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Jun 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is a novel and improved method and apparatus for implementing a latch within an integrated circuit. Data is stored on a storage node via the application of either a first or second state logic source applied through a feedback inverter that maintains the storage node at a particular logic state. During logic transitions from a first state to a second state the storage node is decoupled from the first state logic source via the use of a gating circuit, and the new logic level is applied to the storage node. During logic transitions from the second state to the first state the storage node remains coupled to the second state logic source. The coupling and decoupling of the storage node from the first state logic source is performed via the use of a clock signal that has a non-overlapping cycle with respect to a second clock signal that is used to control the transitions of the state of the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.