Patent · US Expired

Low loss integrated circuit with reduced clock swing

US5854567A · kind A · utility

7Cited by

4References

2Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Stefan Meier · Neubiberg, DE
Erik De Man · Hersbruck, DE

Key dates

Filing date	Sep 24, 1996
Grant date	Dec 29, 1998
Priority date	—
Expiry date	Sep 24, 2016

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0016
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The integrated circuit with a clock system, particularly a CMOS circuit with extensive pipelining, whereby an optimally low overall dissipated power is effected in that a clock driver circuit is provided with a specifically wired driver output stage that generates a clock supply voltage that corresponds to about half the value of a general supply voltage. A great reduction of the dissipated power can be achieved given relative slight sacrifices in the performance capability.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.