Circuit partitioning technique for use with multiplexed inter-connections
US5854752A · kind A · utility
53Cited by
5References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1996 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Jan 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for partitioning a logic circuit is provided for emulation under a virtual wires method using programmable logic devices. Because a virtual wires systems replace pin constraints by a corresponding gate constraint, partitioning for a virtual wires system applies novel constraints and algorithms. In one embodiment, partitioning is provided under a "flat mincut" approach in conjunction with a virtual wire cost constraint. In another embodiment, partitioning is provided under a "hierarchical mincut" in conjunction with a virtual wire cost constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.