Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures
US5854913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1997 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Jun 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two architectures and controls the architectural context under which the microprocessor operates. The control unit controls memory management unit (MMU) hardware that is designed to allow address translation to take place under the control of a mode bit so that the translation mechanism can be switched from one architecture to another. A single MMU translates addresses of the two distinct architectures under control of the mode bit which is also used to simultaneously inform instruction decode which architecture is being used so that instructions are properly decoded. The MMU is also capable of mapping the address translation of one architecture onto that of the other so that software written for both architectures may be multi-tasked under the control of a single operating system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.