Optimizing compiler having data cache prefetch spreading
US5854934A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Dec 29, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of scheduling prefetch instructions in a compiler is described that improves performance by minimizing the performance degradation due to dirty cache misses. The method determines the length N of a loop (step 66). The number of prefetch instructions were M within that loop are then determined (step 68). A prefetch spacing P is then calculated according to the formula P=N/M, where the length of the loop is expressed in cycles (step 70). This prefetch spacing is then attached to each prefetch instruction and the instruction scheduler schedules the prefetch instructions so as to space the prefetch instructions apart by approximately the prefetch spacing P (step 72). After the scheduler arranged for P cycles, a prefetch instruction will be assigned a higher priority for scheduling in the next lot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.