Output circuit for 3V/5V clock chip duty cycle adjustments
US5856753A · kind A · utility
9Cited by
17References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides an analog biased pre-driver and pad as well as a duty cycle adjustment cell prior to the pre-driver and pad. The pre-driver and pad may operate in either a 3 volt mode, a 5 volt mode or any voltage in between depending only on the power supply voltage present. No production configuration or post-production configuration is required. The present invention utilizes a special bias circuit to reduce the Vcc, temperature and other processing variations. A duty cycle cell produces a range of duty cycles when the circuit is operating between a 3 volt and 5 volt range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.