Integrated circuit memory devices including a plurality of row latch circuits and related methods
US5856952A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a semiconductor memory device that has a memory-cell array with memory cells arranged in a matrix, bit-line sense amplifiers connected to bit lines of the memory-cell array, a row address predecoder performing decoding of some of row address signals in response to a system clock, and a plurality of banks having an output line of the row address predecoder in common, includes: a row strobe buffer connected to an external system and producing a first control signal for selecting corresponding banks in response to the system clock, a row address strobe signal, and a bank selection address signal and for controlling generation of a row address sampling control signal; a row address sampling control signal generating circuit producing the row address sampling control signal in a predetermined period of time in response to generation of the first control signal produced by the row strobe buffer in order to control word-line activating and precharging operations; and a row decoder latching an output signal obtained by predecoding a row address with the output signal of the row address sampling control signal generating circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.