Hierarchical bus structure access system
US5857084A · kind A · utility
94Cited by
16References
10Claims
0Family size
Inventor
Key dates
| Filing date | Oct 2, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing the time required to access peripheral devices or to perform peripheral device operations in a multiple bus architecture or hierarchical bus structure environment. A memory device is used to remember which addresses generated responses on which busses. The memory device is accessed in subsequent operations to eliminate the procedure for determining which bus is attached to the desired peripheral.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.