Method and apparatus for addressing extended registers on a processor in a computer system
US5857103A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Jun 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In its various embodiments, the present invention provides a method and apparatus for creating a target executable program from the source code of a target computer program for execution on a target processor. The target processor provided by the method and apparatus has a first set of registers and a second set of registers. Generally, the target processor is capable of executing a first set of instructions which only address the first set of registers. The method and apparatus provides a second set of instruction for the target processor which include a subset of frequently executed instructions within the first set of instructions. These second set of instructions are novel because they able to address both the first set of registers and the second set of registers. A compiler is provided and used for compiling the source code into a number of target executable instructions and allocating the registers on the target processor. The registers within the second set of registers are only allocated to those target executable instructions in the second set of instructions. According to principles of the present invention, the more frequently executed instructions are able to address a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.