Return address adding mechanism for use in parallel processing system
US5857111A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1996 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Feb 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When memory access is to be accomplished in a parallel processing system, interfacing between networks is simplified by generating network control information for the return of read out data in the networks and embedding it into requests. For this purpose, flip-flops for identifying input port numbers are provided in each network through which requests are to be transferred, the identified input numbers are embedded into the requests to be transferred and, when returning data, this information is used as network switching control information. Furthermore, the outputs of arbiters in the networks through which requests are transferred are used as input port numbers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.