Method of manufacturing semiconductor memory device

US5858837A · kind A · utility

Assignee

• NEC CORPORATION · JP

Inventors

• Takashi Sakoh · Kawasaki, JP
• Ichiro Honma · Moriyama, JP

Key dates

• Filing date: Nov 10, 1997
• Grant date: Jan 12, 1999
• Expiry date: Nov 10, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/712

Abstract

A method of manufacturing a semiconductor memory device, comprising the steps of: forming a gate electrode with an insulating spacer, forming a first silicon oxide film by high-temperature chemical vapor deposition (CVD), forming n-type source/drain regions, forming a first insulating interlayer and forming a bit line; forming a second silicon oxide film by low-temperature CVD, forming a BPSG film, and annealing the second silicon oxide film and the BPSG film by first annealing to form a second insulating interlayer constituted by the stacked films; forming a third silicon oxide film by low-temperature CVD, and annealing the third silicon oxide film by second annealing; forming a node contact hole through the annealed third silicon oxide film, the second insulating interlayer, the first insulating interlayer, and the first silicon oxide film; forming an amorphous silicon film doped n-type at the time of the film formation, patterning the amorphous silicon film to form an amorphous silicon film pattern, and removing a native oxide film on a surface of the amorphous silicon film pattern using dilute hydrofluoric acid; and converting the amorphous silicon film pattern into an n-type h…