Successive approximation and shift register without redundancy
US5859608A · kind A · utility
3Cited by
8References
4Claims
0Family size
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Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.