Content addressable memory
US5859791A · kind A · utility
81Cited by
9References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The implementation of two-dimensional decoding, necessary to achieve a reasonable array aspect ratio for a large content addressable memory, is achieved by having multiple match lines per physical row, these match lines being physically routed on top of the array core cell in an upper metal layer. To limit power dissipation in the resulting large-capacity content addressable memory, the match function is implemented by two or more NAND chains per word. Means for achieving the precharging and evaluation of these chains, and for implementing dummy chains for the provision of timing information, are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.