I/O bus expansion system wherein processor checks plurality of possible address until a response from the peripheral selected by address decoder using user input
US5860028A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Feb 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0669
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system including a processor and a peripheral wherein a configuration input of an address decoder or a device address input of a peripheral device which is not needed to set the peripheral's device address is used to increase the input capability of the processor. A data input signal is coupled to the configuration input or to the device address input such that the peripheral has a plurality of possible device addresses dependent on the state of the data input signal. The processor is configured to attempt communication with the peripheral by checking the plurality of possible device addresses of the peripheral until the peripheral gives a response to the processor. The device address to which the peripheral responds represents the state of the data input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.