48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses
US5860076A · kind A · utility
9Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.