Video processor with serialization FIFO
US5860086A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Jun 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.