SRAM write partitioning
US5860118A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for generating a global write enable signal for use in an SRAM partitioning scheme. The global write enable signal is generated by taking a combination of the individual write enable signals and presenting them as a global write control. The global write control signal allows all of the particular data groups to have common timing. The particular SRAM data groups may implement configuration dependent functionality which can be grouped with other data partitions in the array. A particular SRAM data group may share local decode and write control circuitry with other data groups. Particular SRAM data groups not selected for writing have their write data inputs driven to an inactive state during the WRITE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.