Processor with compiler-allocated, variable length intermediate storage
US5860138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1995 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.