Circuit and method for learning attributes of computer memory
US5860140A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Aug 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a circuit and method for learning attributes of computer memory (such as cacheability and writability) in a computer system. The circuit is coupled to a central processing unit ("CPU") and memory units within the computer system. The circuit is capable of retrieving an attribute relating to performance or operation of a particular memory unit when the CPU accesses the particular memory unit and storing the attribute in random-access memory ("RAM") within the circuit, subsequent accesses by the CPU of the memory unit made more efficient by use of the stored attribute. Operation of the circuit is transparent to the CPU and the memory unit. In an alternative embodiment, the circuit is within the CPU itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.