Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate
US5861322A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Jun 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The process includes the following steps: forming a layer of meltable material (102) on an initial substrate (100); forming a first layer of dielectric material (104) and engraving this layer (104) to form openings (106) therein; forming metal blocks (108) in the openings (106); depositing a metal layer (110) covering the blocks; engraving the metal layer (110) to form conducting tracks (112); forming a layer of dielectric material (114) covering the conducting tracks and engraving this layer (114) to form openings therein; forming metal blocks (118) in these openings; separating the interconnection substrate from the initial substrate by heating the meltable material to a temperature equal to or exceeding its melting temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.