Video signal processing device for writing and reading a video signal with respect to a memory according to different clocks, while preventing a write/read address pass-by in the memory
US5861879A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 27, 1996 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Sep 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0407
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An input video signal is written into alternate field memories M1 and M2, according to a timing clock from an input video clock generator. A display video signal is alternately read from those field memories, according to a timing clock from a display video clock generator. In switching a read memory, an address observation circuit judges whether or not a read/write address passes by a write/read address, referring to the condition of reading and writing operations. In this event, the circuit makes a judgement, based on the lag between a vertical synchronizing signals of an input video signal and of a display video signal, and a change of the lag with time. If it is judged that one address will pass by the other, the same read/write memory is again accessed for reading/writing. With this arrangement, there is provided a circuit having a relatively simple structure for preventing a match of read and write addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.