Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations
US5862067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for combining at least two packed multiply-accumulate instructions (or equivalent operations) to compute a filter result from coefficients having more bits than can be processed by a single multiply-accumulate instruction (or equivalent operation). This achieves greater accuracy in computing transforms and digital filters without requiring more expensive hardware to implement multiply-accumulate instructions for larger operands. Typical applications are compression/decompression algorithms, modem, audio and video. The invention is scalable, permitting additional multiply-accumulate instructions to be added as incrementally larger coefficients are required. Additionally, the invention permits different numbers of multiply-accumulate instructions for each coefficient depending on the sensitivity to that particular coefficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.