Memory accessible in read mode only
US5862091A · kind A · utility
10Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1997 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Jul 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory accessible in read mode only comprises storage elements designed to contain a bit that can assume two levels. Each memory cell comprises a transistor. The transistor of the storage element may include an associated circuit portion to prompt a short circuit between the drain and the source of the transistor if the storage element has to contain one bit at one of the two levels. Furthermore, the use of an unbalanced differential amplifier permits an improvement of the access time of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.