Non-volatile programmable memory having a buffering capability and method of operation thereof
US5862099A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Jan 19, 1999 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessible to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.